Setup time, Hold time, clk skew, clk jitter, Metastability (Updating)

One method of clk generation

1) Setup time

2) Hold time

Device Switching is fastest at low temperatures.
The timing analysis are done at extreme corners to ensure that they meet the timing specs.
a. Fastest case: Fast N and Fast P transistors, High Vdd, Low Temperature
b. Slowest Case: Slow N and Slow P transistors, low Vdd, High Temperature

This isn't necessarily true in all cases. In some process technologies there is a phenomenon called temperature inversion.
3) Clock Skew
Skew is the difference in arrival of clock at two consecutive pins of a sequential element is called skew. Clock skew is the variation at arrival time of clock at destination points in the clock network. The difference in the arrival of clock signal at the clock pin of different flops.

If capture clock comes late than launch clock then it is called positive skew. When data and clock are routed in same direction then it is Positive skew.

Positive skew can lead to hold violation.

Positive skew improves setup time.

link

4) Clock Jitter
Introduction
Jitter is the timing variations of a set of signal edges from their ideal values. Jitters in clock
signals are typically caused by noise or other disturbances in the system. Contributing factors
include thermal noise, power supply variations, loading conditions, device noise, and
interference coupled from nearby circuits.

Types of Jitter
Jitter can be measured in a number of ways; the following are the major types of jitter:
• Period Jitter
• Cycle to Cycle Period Jitter
• Long Term Jitter
• Phase Jitter
• Time Interval Error (TIE)

5) Comparison of Clock skew and Clock jitter

Clock skewThe deterministic (knowable) difference in clock arrival times at each flip-flop
Caused mainly  by imperfect balancing of clock tree/mesh
Can be deliberately introduced using delay blocks in order  to time-borrow
Accounted for in STA by calculating the clock arrival times at each flip-flop

Clock jitterThe random (unknowable, except distribution s) difference in clock arrival times at each flip-flop Caused by on-die process, Vdd, temperature variation, PLL jitter, crosstalk, Static timing analysis (STA) accuracy, layout parameter extraction (LPE) accuracyAccounted for in STA by subtracting (~3 s) from the cycle time in long path analysis, and adding to receiving clock arrival time in race analysis

Jitter is always bad, skew can be helpful or harmful.

Clock uncertainty D º skew ± jitter

6) Clock gating

Gated clocks

Clock signals that are passed through some gate other than buffer and inverters are called gated clocks. These clock signals will be under the control of gated logic. Clock gating is used to turn off clock to some sections of design to save power. Click here to read more about clock gating.

Click here for more details

7） Hazard