NAND, Gates, Mux

Mux related:

                       Using Mux to design gates






















Using NAND gates to design other gates

Some VLSI questions and anwsers

1）Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared to PMOS transistors.

2）What is Channel-length modulation?

The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. Therefore I_D' = I_D *(1+LAMBDA*V_DS); Lambda is the channel length modulation and is generally proportional to the inverse of the channel length. Channel length modulation is more pronounced in short channel devices. Also, Short channel devices are prone to velocity saturation.Velocity saturation occurs when the horizontal component of the E-field (along the channel) reaches a critical value. At this point the carriers collide.

3）What is Latch – up?

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

4） How do you prevent latch up problem?
Latch up problem can be reduced by reducing the gain of parasitic transistors and resistors. It can be prevented in 2 ways
• Latch up resistant CMOS program
• Layout technique
The various lay out techniques are
Internal latch up prevention technique
I/O latch up prevention technique.

5）What is Stick Diagram? It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.

What are the uses of Stick diagram? It can be drawn much easier and faster than a complex layout. These are especially important tools for layout built from large cells.

Give the various color coding used in stick diagram? Green – n-diffusion；Red- polysilicon；Blue –metal；Yellow- implant；Black-contact areas.

6）Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

7) What is Body effect?
The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.

8) Compare nMOS and pMOS devices

                                   nMOS                                                                       pMOS
A section of p-type separating 2 n-type silicon          A section of n-type separating 2 p type silicon
Turns ON with the gate at logic 1                               Turns ON with the gate at logic 0
Majority carriers are electrons                                    Majority carriers are holes
Good transmission of logic 0                                       Good transmission of logic 1

9) What is meant by a transmission gate?
A transmission gate consists of an n-channel transistor and p-channel transistor with separate gates and common source and drain. 

10) Define Rise time and fall time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

11) Define Delay time
Delay time, td is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output.

12) Define Noise Margin

The parameter which gives the quantitative measure of how stable the inputs are with respect to coupled electromagnetic signal interference.
NML = Vil-Vol
NMH = Voh-Vih

13) What is a task in verilog, AND difference between task and funtion?

A task is like a procedure, it provides the ability to execute common pieces of code from several different places in a description;

Functions always return a single value. with in a function, no event, delay or timing control statements are permitted, at least one input argument and they cannot have output or inout arguments. Functions is unable to enable a task however it can enable other functions. Tasks don’t return a value, but can pass multiple values through output and inout arguments.Tasks can enable a function as well as other versions of tasks.

14) Mention few data types in Verilog

Nets, registers, vectors, numbers and arrays

15) Mention the four key words used for looping in verilog

while, for, repeat, forever

16) Specify the operator which have highest and lowest precedence.

Unary operator – highest precedence
Conditional operator – lowest precedence

17) Give the examples  for Procedural statement and control flow.
Loop statement , Wait statement, Conditional statement, Case statement

18) Blocking and non-blocking statements differ in executing the statements . How?

They are two types of procedural assignments. Blocking statements are executed in the order in which they are specified in a sequential block. “= “is the operator used to specify blocking assignments. Blocking assignment executes sequentially and usually use Blocking statement for combinational logic. evaluation and assignment are immediately.

Non blocking statements allow scheduling of assignments without blocking execution of the statement that follow in a sequential block. “<=” is the operator used to specify non blocking assignment. For non-blocking assignment, the right hand side statement is evaluated and stored first then been assigned to the left hand side. assignment is postponed until rhs evaluations are done.
Using two ways to swap the content of two registers:
always@(posedge clk) begin                                     always@(posedge clk) begin
    temp=b;                                                                       a<=b;                  
    b = a;                                                                            b<=a;    
    a = temp;                                                              end
end

19) What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling

20) What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

21) What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches.

22) Give the two blocks in behavioral modeling.
1. An initial block executes once in the simulation and is used to set up
initial conditions and step-by-step data flow
2. An always block executes in a loop and repeats during the simulation.

23) Value levels Condition in hardware circuits
Verilog supports four levels for the values needed to describe hardware referred to as value sets.

0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state

24) Different bitwise operators. Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two
^ Bitwise xor Two
^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two

24) Different arithmetic operators. Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
** Power (exponent) Two

25) What are the types of conditional statements?
1. No else statement
Syntax : if ( [expression] ) true – statement;
2. One else statement
Syntax : if ( [expression] ) true – statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

26) What is meant by continuous assignment statement in verilog HDL?

Power Consumption (Updating)

Two components determine the power consumption in a CMOS circuit:

1. Static power consumption: input not switching

•       sub-threshold current;
•       gate leakage

      P_s = V_cc* I_cc

2. Dynamic power consumption: input switching

•       short circuit. current from V_dd to GND
•       switching circuit. charge or discharge output capacitance. P=Cout * V_cc^2

Counter and Divider

Asynchronous Counter
Asynchronous counters, also known as ripple counters, are not clocked by a common pulse and hence every flip-flop in the counter changes at different times. The flip-flops in an asynchronous counter is usually clocked by the output pulse of the preceding flip-flop. The first flip-flop is clocked by an external event. A synchronous counter however, has an internal clock, and the external event is used to produce a pulse which is synchronized with this internal clock. The diagram of an ripple counter is shown below.
Verilog Code and Test Bench

Synchronous Counter
Following is one kind of synchronous counter

Comparison

Advantages:

Asynchronous counter requires less circuitry and is easier to construct.

    Disadvantages:

   1) The asynchronous counter is slow. In a synchronous counter, all the flip-flops will change states simultaneously while for an asynchronous counter, the propagation delays of the flip-flops add together to produce the overall delay. Hence, the more bits or number of flip-flops in an asynchronous counter, the slower it will be.

   2) Secondly, there are certain "risks" when using an asynchronous counter. In a complex system, many state changes occur on each clock edge and some ICs respond faster than others. If an external event is allowed to affect a system whenever it occurs (unsynchronized), there is a small chance that it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. And the worse this is that these problems are difficult to foresee and test for because of the random time difference between the events.

Divide by three                                                                  Verilog code for divide by 3 any duty

Module divide3(input clk, input rst, output out);

    Parameter s0 = 2'00; s1=2'01; s2 = 2'10;

    reg[1:0] state, nextstate;

    always@(posedge clk) begin

        if(rst) state<= s0;

        else state<= nextstate;

    end

    always@(*) begin

        case(state):

                s0: nextstate = s1;

                s1: nextstate = s2;

                s2: nextstate = s0;

                default: nextstate = s2;

        endcase

    end

assign out = (state==s0);

end module
Another Verilog Code for divide by 3 with 50% duty cycle

RTL Code ----- Fibonacci Sequence

Write the Fibonacci Sequence using Verilog HDL:

module fib(input clock, input rst, input [5:0] n, output reg ready, output [31:0] value)

reg [31:0] previous, current;

reg [5:0] counter;




// Reset the circuit

always @(posedge clk)

if(rst) begin

previous <= 32'd0;

current <= 32'd1;

counter <= 32'd0;

end



// Compute next Fibonacci number

always @(posedge clock)

begin

// Increment current index

counter <= counter + 1;



// Efficient adders are automatically inferred

current <= current + previous;

previous <= current;



if (counter == n)

ready <= 1;

end



// Read the value of the nth fibonacci number from the internal register

assign value = current;



endmodule

RAM (Especially SRAM) (Updating)

SRAM

Suppose the drain of M1 is called point A; the drain of M5 is called point B.

Read: Both bitlines start at Vdd (Precharged), cell pulls one down;
Suppose now A=VDD, B=GND;
M1 and M4 are cut off;
1) M2 and M3 are both pulling up, there would be no sizing constrains;
2) M5 is in triode and is pulling down, M6 is in saturation and is pulling up;
3) M5 must win to avoid flipping the cell.

Write: One bitline is pulled low, low bitline value overpowers cell;
Suppose still now A=VDD, B=GND; bitline is pulled down to GND, bitline_bar stays at high
M1 and M4 are cut off;
(1) Write a low:   M2 and M3 are both in triode, M2 must overwrite M4;
(2) Write a hight: M5 is in triode, M6 is in saturation, M6 must overwrite M1, this condition is contradict with the condition in READ mode.

DRAM

FIFO and LIFO(Updating)

FIFO

1)SYNCHRONOUS and ASYNCHRONOUS;
   If read and write clock domains are governed by same clock signal, whether one clock signal or two clock signals, the FIFO is said to be SYNCHRONOUS;
   If read and write clock domains are not governed by clock signals FIFO is said to be ASYNCHRONOUS. 

2) Here is an example of Implement FIFI using Verilog

3) FIFO Depth Calculation

Traffic Light(Updating)

1) The simple traffic light in a two way road.
     So there are two traffic lights 1 and 2 and each has green 1 and red 0;
                                                T1    T2
                                        S0     0       0
                                        S1     1       0
                                        S2     0       1
   促使state转变的：
1）input （not clock）
2）next clock edge

Delay in the graph is the key in the problem. In this case, we can generate another input signal as input.


2) A more complex traffic light

Latch and Flip-Flop Design

Latch
Function: Data will be transferred as long as the clk is at positive high.

Graph 1) is the basic MUX-based Latch

Graph 2) has an additional keeper .
    The feedback inverter should be smaller to enable faster propagation of D

Graph 3) is the back-driving version.
    Also called TG-Latch
    Clk=1: D is transferred to A and then Q;
    Clk=0: D can't be propagate, old value is stored at A;
    No write conflict;
    The inverter at D is used for input noice protection.

Graph 4) used when the output is driven to noisy circuits.

Graph 1) to 4) are all static Latch.

Graph 5) is Dynamic Latch.

Take a look the waveform of clk, D and Q, the setup/hold time is w.r.t. the closing CLK edge!











Flip-Flop
Function: Data will be transferred at only one or both of the clk edges.

Graph 1) a pair of back to back latches, note the fi and fi_bar in the first graph should be exchanged.

Graph 2) The Master-Slave Latch Pair(MS Flip-Flop).
    Clk=0: master passes D to S;
    Clk=1: slave passes S to Q;
    D arrives just before clk: 0->1

Graph 3) The block representation of the pulse triggered Latch. (Need to be better analyzed)

Graph 4)The waveform of a flip-flop. The setup and hold time are all w.r.t. the rising edge if it is a posedge triggered flip-flop.



















Important Knowledge
Two ways are usually used to build storage elements:
1) using positive feedback to keep the value;
2) using capacitance to dynamically store the value;
    Adv  : faster
    Disad: less robust, sensitive to noise, particularly charge injection and charge sharing;
(Need to know what is charge sharing)

Reference: Course Notes