Showing posts with label SRAM. Show all posts
Showing posts with label SRAM. Show all posts

Monday, February 24, 2014

RAM (Especially SRAM) (Updating)

SRAM


Suppose the drain of M1 is called point A; the drain of M5 is called point B.

Read: Both bitlines start at Vdd (Precharged), cell pulls one down;
Suppose now A=VDD, B=GND;
M1 and M4 are cut off;
1) M2 and M3 are both pulling up, there would be no sizing constrains;
2) M5 is in triode and is pulling down, M6 is in saturation and is pulling up;
3) M5 must win to avoid flipping the cell.

Write: One bitline is pulled low, low bitline value overpowers cell;
Suppose still now A=VDD, B=GND; bitline is pulled down to GND, bitline_bar stays at high
M1 and M4 are cut off;
(1) Write a low:   M2 and M3 are both in triode, M2 must overwrite M4;
(2) Write a hight: M5 is in triode, M6 is in saturation, M6 must overwrite M1, this condition is contradict with the condition in READ mode.

DRAM