Latch and Flip-Flop Design

Latch
Function: Data will be transferred as long as the clk is at positive high.

Graph 1) is the basic MUX-based Latch

Graph 2) has an additional keeper .
    The feedback inverter should be smaller to enable faster propagation of D

Graph 3) is the back-driving version.
    Also called TG-Latch
    Clk=1: D is transferred to A and then Q;
    Clk=0: D can't be propagate, old value is stored at A;
    No write conflict;
    The inverter at D is used for input noice protection.

Graph 4) used when the output is driven to noisy circuits.

Graph 1) to 4) are all static Latch.

Graph 5) is Dynamic Latch.

Take a look the waveform of clk, D and Q, the setup/hold time is w.r.t. the closing CLK edge!











Flip-Flop
Function: Data will be transferred at only one or both of the clk edges.

Graph 1) a pair of back to back latches, note the fi and fi_bar in the first graph should be exchanged.

Graph 2) The Master-Slave Latch Pair(MS Flip-Flop).
    Clk=0: master passes D to S;
    Clk=1: slave passes S to Q;
    D arrives just before clk: 0->1

Graph 3) The block representation of the pulse triggered Latch. (Need to be better analyzed)

Graph 4)The waveform of a flip-flop. The setup and hold time are all w.r.t. the rising edge if it is a posedge triggered flip-flop.



















Important Knowledge
Two ways are usually used to build storage elements:
1) using positive feedback to keep the value;
2) using capacitance to dynamically store the value;
    Adv  : faster
    Disad: less robust, sensitive to noise, particularly charge injection and charge sharing;
(Need to know what is charge sharing)

Reference: Course Notes