Counter and Divider

Asynchronous Counter
Asynchronous counters, also known as ripple counters, are not clocked by a common pulse and hence every flip-flop in the counter changes at different times. The flip-flops in an asynchronous counter is usually clocked by the output pulse of the preceding flip-flop. The first flip-flop is clocked by an external event. A synchronous counter however, has an internal clock, and the external event is used to produce a pulse which is synchronized with this internal clock. The diagram of an ripple counter is shown below.
Verilog Code and Test Bench

Synchronous Counter
Following is one kind of synchronous counter

Comparison

Advantages:

Asynchronous counter requires less circuitry and is easier to construct.

    Disadvantages:

   1) The asynchronous counter is slow. In a synchronous counter, all the flip-flops will change states simultaneously while for an asynchronous counter, the propagation delays of the flip-flops add together to produce the overall delay. Hence, the more bits or number of flip-flops in an asynchronous counter, the slower it will be.

   2) Secondly, there are certain "risks" when using an asynchronous counter. In a complex system, many state changes occur on each clock edge and some ICs respond faster than others. If an external event is allowed to affect a system whenever it occurs (unsynchronized), there is a small chance that it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. And the worse this is that these problems are difficult to foresee and test for because of the random time difference between the events.

Divide by three                                                                  Verilog code for divide by 3 any duty

Module divide3(input clk, input rst, output out);

    Parameter s0 = 2'00; s1=2'01; s2 = 2'10;

    reg[1:0] state, nextstate;

    always@(posedge clk) begin

        if(rst) state<= s0;

        else state<= nextstate;

    end

    always@(*) begin

        case(state):

                s0: nextstate = s1;

                s1: nextstate = s2;

                s2: nextstate = s0;

                default: nextstate = s2;

        endcase

    end

assign out = (state==s0);

end module
Another Verilog Code for divide by 3 with 50% duty cycle