C++ OOP Knowledge

1. 类（Class）与 对象（Object）的关系 就是具体（Concrete）与（Abstract）的关系

2. 构造函数（constructor）

     构造函数的函数名和相应的类名相同。构造函数没有任何返回值，也不加void; 一个类可以不包含构造函数，此时当类的对象被定义时，编译器会自动定义一个默认构造函数; 构造函数必须要保证一旦一个对象被构造，类中的所有数据成员都有合理的定义好的值。
     Constructors are recognized by their names which is equal to the class name. Constructors do not specify return type, not even void.
     It is possible to define a class lacking any constructors. In that case the compiler defines a default constructor that is called when an object of that class is defined.
     Constructors must ensure that all the class's data members have sensible or as-least well-defined values once the object has been construct.

     1）默认构造函数（default constructor）；Default constructor has no argument.
     2）构造函数可以不带任何参数；
     3）构造函数可以带有默认参数，参数的个数可以任意；
     4）构造函数的重载（overload of constructor)：一个类有多个不同参数形式及参数类型不同的构造函数；
     Example： Class point;
                        构造函数: point();
                                          point(double x, double y);

     5）拷贝构造函数 （Copy Constructor）：作用是用一个已经存在的对象来初始化该类的对象；用户可以根据需要定义拷贝构造函数，也可以由系统生成一个默认拷贝构造函数.

     A copy constructor is a special constructor for a class/struct that is used to make a copy of an existing instance.        According to the C++ standard, the copy constructor for MyClass must have one of the following signatures:
    MyClass( const MyClass& other );
    MyClass( MyClass& other );
    MyClass( volatile const MyClass& other );
  MyClass( volatile MyClass& other );    Myclass p1;
    Myclass p2(p1); //copy constructor is called;
    
    Copy Constructor is called in following three ways:
    1) Using an object of the class to instantiate another object;
    2) The formal parameter of a function is an object of a class. The copy constructor is called when the formal parameter and the actual parameter are combined;
    3) The return value of a function is an object of a class. The copy constructor is called when the function is completed and the return the caller.
     6）默认拷贝构造函数(Default Copy Constructor)：当用一个已经存在的对象初始化本类的新对象时，如果没有自定义拷贝构造函数，则系统会自动生成一个默认的拷贝构造函数来完成初始化的工作。
          When using an existing object to instantiate a new object, if there is no self-defined copy constructor, the system will automatically generate a default copy constructor to complete the instantiation. 


3. 析构函数
    也是一种特殊的成员函数，也被声明为共有成员。析构函数的作用是释放分配给对象的内存空间。 The function of the destructor is to release the memory space that is allocated to objects.
    Destructor has no parameters, no return value, can not be reloaded. There can only be one destructor.

4.  友元（Friend）
    1）友元函数（Friend Function）
             友元函数不是当前类的成员函数，而是独立于当前类的外部函数；它可以是普通函数或其他类的成员函数。            友元函数使用前必须要在类定义时声明，声明是在其函数名前加上关键字friend。友元函数的定义一般在外部进行，不需要在其名字前加class::. 友元函数不是类的成员，不能直接引用对象成员的名字，也不能通过this指针引用对象成员，必须通过作为入口参数传递进来的对象名或对象指针来引用该对象的成员。       
 class point{                friend double dist(point &p1, point &p2);}
 double dist(point &p1, point &p2){}
        当一个函数需要访问多个类时，应该把这个函数同时定义为这些类的友元函数。    2）友元成员 （friend member function）
            当一个类的成员函数是另一个类的友元函数，则称这个成员函数为友元成员。通过友元成员函数，不仅可以访问自己所在类对象中的私有和公有成员，还可以访问由关键字friend 声明语句所在的类对象中的私有和公有成员。    3）友元类（Friend Class）
            当一个类作为另一个类的友元时，称这个类为友元类。这个类的所有成员函数都成为另一个类的友元函数。 因此，友元类中的所有成员函数都可以通过对象名直接访问另一个类中的私有成员。友元类的声明可以放在类声明中的任何位置。


5. 继承与派生（Inheritance and Derivation）
Base\继承方式      Public                  Private                  Protected    
Private                  private                 不可访问               不可访问    
Public                   public                     private                  protected     
Protected              protected                 private                  protected      
      1) 派生函数的构造函数            派生类的数据成员由 所有基类的数据成员，派生类新增的数据成员共同组成，如果派生类新增成员中还有对象成员，那派生类的数据成员中还间接含有这些对象的数据成员。因为对派生类对象初始化，就要对基类数据成员，新增数据成员和对象成员的数据进行初始化。           
 <派生类名>：：<派生类名> （参数总表）：基类名（参数表)，对象成员名1（参数表1），..., 对象成员名n（参数表n）{                        //派生类新增成员的初始化语句            } 
      2）派生函数的析构函数
            析构函数不能被继承，如果需要，则在派生类中重新定义。      
      3）构造和析构的顺序
            构造：先base再derivation；            析构：先derivation再base；


6. 多重继承(Multiple Inheritance）
      1）二义性问题（ambiguity）
            当多重继承（有多个基类）以及多个基类中有同名成员时，会产生二义性问题            解决方法：                 
 1）使用作用域运算符“::” ， 指定相应的基类                  
2）使用同名覆盖额原则在派生类中重新定义与基类中同名的成员（如果是成员函数，则参数表也要相同，参数不同的情况为重载）以隐蔽掉基类的同名成员，在引用这些同名的成员时，就是使用派生类中的函数。                  
3） 使用虚函数，具体方法见“7.虚基类”的解释。


7. 虚基类（Virtual Base Class）
      虚基类引入的作用：解决基类中由于同名成员的问题而产生的二义性 
      1）base1继承了base，base2继承了base，那就可以把base定义为虚基类，继承时应该这样写      
class base1: virtual public base{
      }      
class base2: virtual public base{
      }


8. 多态（Polymorphism）
      多态就是同一个函数名称，作用在不同的对象上将产生不同的操作。就是“一个接口，多种实现”，就是同一种事物表现出的多种形态。
      多态包括：重载多态，强制多态，包含多态，参数多态
      包含多态：定义于不同类中的同名成员函数的多态行为，主要通过虚函数来实现；

      多态的实现方式： 1）编译时的多态；2）运行时的多态。
       1）编译时的多态/静态多态性， 由静态联编支持的，用函数重载和运算符重载来实现；
       2）运行时的多态/动态多态性，由动态联编支持的， 用继承和虚函数来实现;
       3） 虚函数的定义在基类中进行 在原先定义的函数名和返回type前加 virtual

              重载虚函数： 要求函数名、返回类型、参数个数、参数的类型和参数的顺序必须与基类中的虚函数的原型完全相同；
              析构函数也可以声明成虚函数，只要在“~”前加上virtual；
              一个虚函数无论被继承多少次，仍保持其虚函数的特性，与继承次数无关

9. 抽象类（Abstract Class）多态的一种
       抽象类为类提供统一的操作界面，简历抽象类的原因就是为了通过抽象类多态使用其中的成员函数，抽象类是带有纯虚函数的类。

     1）纯虚函数（Pure Virtual Function）
            在积累中不能为虚函数给出一个有意义的实现时，可以将其声明为纯虚函数。 纯虚函数的具体实现可以留给派生类完成。纯虚函数的作用是为派生类提供一个一致的接口（A consistent interface）。
            纯虚函数： virtual void set（）= 0
      2） 抽象类
            带有纯虚函数的类称为抽象类，抽象类不能定义对象。
            实际中，为了强调一个类是抽象类，可以将该类的构造函数说明为保护的访问控制权限

NAND, Gates, Mux

Mux related:

                       Using Mux to design gates






















Using NAND gates to design other gates

Setup time, Hold time, clk skew, clk jitter, Metastability (Updating)

One method of clk generation

1) Setup time

2) Hold time

Device Switching is fastest at low temperatures.
The timing analysis are done at extreme corners to ensure that they meet the timing specs.
a. Fastest case: Fast N and Fast P transistors, High Vdd, Low Temperature
b. Slowest Case: Slow N and Slow P transistors, low Vdd, High Temperature

This isn't necessarily true in all cases. In some process technologies there is a phenomenon called temperature inversion.
3) Clock Skew
Skew is the difference in arrival of clock at two consecutive pins of a sequential element is called skew. Clock skew is the variation at arrival time of clock at destination points in the clock network. The difference in the arrival of clock signal at the clock pin of different flops.

If capture clock comes late than launch clock then it is called positive skew. When data and clock are routed in same direction then it is Positive skew.

Positive skew can lead to hold violation.

Positive skew improves setup time.

link

4) Clock Jitter
Introduction
Jitter is the timing variations of a set of signal edges from their ideal values. Jitters in clock
signals are typically caused by noise or other disturbances in the system. Contributing factors
include thermal noise, power supply variations, loading conditions, device noise, and
interference coupled from nearby circuits.

Types of Jitter
Jitter can be measured in a number of ways; the following are the major types of jitter:
• Period Jitter
• Cycle to Cycle Period Jitter
• Long Term Jitter
• Phase Jitter
• Time Interval Error (TIE)

5) Comparison of Clock skew and Clock jitter

Clock skewThe deterministic (knowable) difference in clock arrival times at each flip-flop
Caused mainly  by imperfect balancing of clock tree/mesh
Can be deliberately introduced using delay blocks in order  to time-borrow
Accounted for in STA by calculating the clock arrival times at each flip-flop

Clock jitterThe random (unknowable, except distribution s) difference in clock arrival times at each flip-flop Caused by on-die process, Vdd, temperature variation, PLL jitter, crosstalk, Static timing analysis (STA) accuracy, layout parameter extraction (LPE) accuracyAccounted for in STA by subtracting (~3 s) from the cycle time in long path analysis, and adding to receiving clock arrival time in race analysis

Jitter is always bad, skew can be helpful or harmful.

Clock uncertainty D º skew ± jitter

6) Clock gating

Gated clocks

Clock signals that are passed through some gate other than buffer and inverters are called gated clocks. These clock signals will be under the control of gated logic. Clock gating is used to turn off clock to some sections of design to save power. Click here to read more about clock gating.

Click here for more details

7） Hazard

Some VLSI questions and anwsers

1）Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared to PMOS transistors.

2）What is Channel-length modulation?

The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. Therefore I_D' = I_D *(1+LAMBDA*V_DS); Lambda is the channel length modulation and is generally proportional to the inverse of the channel length. Channel length modulation is more pronounced in short channel devices. Also, Short channel devices are prone to velocity saturation.Velocity saturation occurs when the horizontal component of the E-field (along the channel) reaches a critical value. At this point the carriers collide.

3）What is Latch – up?

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

4） How do you prevent latch up problem?
Latch up problem can be reduced by reducing the gain of parasitic transistors and resistors. It can be prevented in 2 ways
• Latch up resistant CMOS program
• Layout technique
The various lay out techniques are
Internal latch up prevention technique
I/O latch up prevention technique.

5）What is Stick Diagram? It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.

What are the uses of Stick diagram? It can be drawn much easier and faster than a complex layout. These are especially important tools for layout built from large cells.

Give the various color coding used in stick diagram? Green – n-diffusion；Red- polysilicon；Blue –metal；Yellow- implant；Black-contact areas.

6）Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

7) What is Body effect?
The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.

8) Compare nMOS and pMOS devices

                                   nMOS                                                                       pMOS
A section of p-type separating 2 n-type silicon          A section of n-type separating 2 p type silicon
Turns ON with the gate at logic 1                               Turns ON with the gate at logic 0
Majority carriers are electrons                                    Majority carriers are holes
Good transmission of logic 0                                       Good transmission of logic 1

9) What is meant by a transmission gate?
A transmission gate consists of an n-channel transistor and p-channel transistor with separate gates and common source and drain. 

10) Define Rise time and fall time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

11) Define Delay time
Delay time, td is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output.

12) Define Noise Margin

The parameter which gives the quantitative measure of how stable the inputs are with respect to coupled electromagnetic signal interference.
NML = Vil-Vol
NMH = Voh-Vih

13) What is a task in verilog, AND difference between task and funtion?

A task is like a procedure, it provides the ability to execute common pieces of code from several different places in a description;

Functions always return a single value. with in a function, no event, delay or timing control statements are permitted, at least one input argument and they cannot have output or inout arguments. Functions is unable to enable a task however it can enable other functions. Tasks don’t return a value, but can pass multiple values through output and inout arguments.Tasks can enable a function as well as other versions of tasks.

14) Mention few data types in Verilog

Nets, registers, vectors, numbers and arrays

15) Mention the four key words used for looping in verilog

while, for, repeat, forever

16) Specify the operator which have highest and lowest precedence.

Unary operator – highest precedence
Conditional operator – lowest precedence

17) Give the examples  for Procedural statement and control flow.
Loop statement , Wait statement, Conditional statement, Case statement

18) Blocking and non-blocking statements differ in executing the statements . How?

They are two types of procedural assignments. Blocking statements are executed in the order in which they are specified in a sequential block. “= “is the operator used to specify blocking assignments. Blocking assignment executes sequentially and usually use Blocking statement for combinational logic. evaluation and assignment are immediately.

Non blocking statements allow scheduling of assignments without blocking execution of the statement that follow in a sequential block. “<=” is the operator used to specify non blocking assignment. For non-blocking assignment, the right hand side statement is evaluated and stored first then been assigned to the left hand side. assignment is postponed until rhs evaluations are done.
Using two ways to swap the content of two registers:
always@(posedge clk) begin                                     always@(posedge clk) begin
    temp=b;                                                                       a<=b;                  
    b = a;                                                                            b<=a;    
    a = temp;                                                              end
end

19) What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling

20) What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

21) What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches.

22) Give the two blocks in behavioral modeling.
1. An initial block executes once in the simulation and is used to set up
initial conditions and step-by-step data flow
2. An always block executes in a loop and repeats during the simulation.

23) Value levels Condition in hardware circuits
Verilog supports four levels for the values needed to describe hardware referred to as value sets.

0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state

24) Different bitwise operators. Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two
^ Bitwise xor Two
^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two

24) Different arithmetic operators. Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
** Power (exponent) Two

25) What are the types of conditional statements?
1. No else statement
Syntax : if ( [expression] ) true – statement;
2. One else statement
Syntax : if ( [expression] ) true – statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

26) What is meant by continuous assignment statement in verilog HDL?

[LEETCODE] Sort Colors

[LEETCODE] Sort Colors

Given an array with n objects colored red, white or blue, sort them so that objects of the same color are adjacent, with the colors in the order red, white and blue.

Here, we will use the integers 0, 1, and 2 to represent the color red, white, and blue respectively.

思路:

定义一个red指针在最左，一个blue指针在最右。

一个变量从0开始向blue指针扫描：

遇到red(0)  就跟red 指针对换，red 指向下一个，扫描变量指向下一个；

遇到blue(2)就跟blue指针对换，blue指向前一个，扫描变量不动，因为需要判断被换了的值。

代码:

An one-pass algorithm using only constant space

    void sortColors(int A[], int n) {

        int red  =0  ;

        int blue =n-1;

        int i=0;

        while(i<blue+1){

            if(A[i] == 0){

                std::swap(A[red], A[i]);

                red++;

                i++;

                continue;

            }

            if(A[i] == 2){

                std::swap(A[blue],A[i]);

                blue--;

                continue;

            }

            i++;

        }

    }

Linux Learning

Basic commands

Basic command

Go back to previous directory: cd ../  or cd../../  and so on

TCP/IP Learning (Updating)

1. TCP 3-way Handshake (SYC, SYC-ACK, ACK)
Link to the detailed analysis

Power Consumption (Updating)

Two components determine the power consumption in a CMOS circuit:

1. Static power consumption: input not switching

•       sub-threshold current;
•       gate leakage

      P_s = V_cc* I_cc

2. Dynamic power consumption: input switching

•       short circuit. current from V_dd to GND
•       switching circuit. charge or discharge output capacitance. P=Cout * V_cc^2

Counter and Divider

Asynchronous Counter
Asynchronous counters, also known as ripple counters, are not clocked by a common pulse and hence every flip-flop in the counter changes at different times. The flip-flops in an asynchronous counter is usually clocked by the output pulse of the preceding flip-flop. The first flip-flop is clocked by an external event. A synchronous counter however, has an internal clock, and the external event is used to produce a pulse which is synchronized with this internal clock. The diagram of an ripple counter is shown below.
Verilog Code and Test Bench

Synchronous Counter
Following is one kind of synchronous counter

Comparison

Advantages:

Asynchronous counter requires less circuitry and is easier to construct.

    Disadvantages:

   1) The asynchronous counter is slow. In a synchronous counter, all the flip-flops will change states simultaneously while for an asynchronous counter, the propagation delays of the flip-flops add together to produce the overall delay. Hence, the more bits or number of flip-flops in an asynchronous counter, the slower it will be.

   2) Secondly, there are certain "risks" when using an asynchronous counter. In a complex system, many state changes occur on each clock edge and some ICs respond faster than others. If an external event is allowed to affect a system whenever it occurs (unsynchronized), there is a small chance that it will occur near a clock transition, after some IC's have responded, but before others have. This intermingling of transitions often causes erroneous operations. And the worse this is that these problems are difficult to foresee and test for because of the random time difference between the events.

Divide by three                                                                  Verilog code for divide by 3 any duty

Module divide3(input clk, input rst, output out);

    Parameter s0 = 2'00; s1=2'01; s2 = 2'10;

    reg[1:0] state, nextstate;

    always@(posedge clk) begin

        if(rst) state<= s0;

        else state<= nextstate;

    end

    always@(*) begin

        case(state):

                s0: nextstate = s1;

                s1: nextstate = s2;

                s2: nextstate = s0;

                default: nextstate = s2;

        endcase

    end

assign out = (state==s0);

end module
Another Verilog Code for divide by 3 with 50% duty cycle

RTL Code ----- Fibonacci Sequence

Write the Fibonacci Sequence using Verilog HDL:

module fib(input clock, input rst, input [5:0] n, output reg ready, output [31:0] value)

reg [31:0] previous, current;

reg [5:0] counter;




// Reset the circuit

always @(posedge clk)

if(rst) begin

previous <= 32'd0;

current <= 32'd1;

counter <= 32'd0;

end



// Compute next Fibonacci number

always @(posedge clock)

begin

// Increment current index

counter <= counter + 1;



// Efficient adders are automatically inferred

current <= current + previous;

previous <= current;



if (counter == n)

ready <= 1;

end



// Read the value of the nth fibonacci number from the internal register

assign value = current;



endmodule

RAM (Especially SRAM) (Updating)

SRAM

Suppose the drain of M1 is called point A; the drain of M5 is called point B.

Read: Both bitlines start at Vdd (Precharged), cell pulls one down;
Suppose now A=VDD, B=GND;
M1 and M4 are cut off;
1) M2 and M3 are both pulling up, there would be no sizing constrains;
2) M5 is in triode and is pulling down, M6 is in saturation and is pulling up;
3) M5 must win to avoid flipping the cell.

Write: One bitline is pulled low, low bitline value overpowers cell;
Suppose still now A=VDD, B=GND; bitline is pulled down to GND, bitline_bar stays at high
M1 and M4 are cut off;
(1) Write a low:   M2 and M3 are both in triode, M2 must overwrite M4;
(2) Write a hight: M5 is in triode, M6 is in saturation, M6 must overwrite M1, this condition is contradict with the condition in READ mode.

DRAM

MOS Transistors

NMOS Transistor
CMOS





P-N Junction：
forward bias: p->n
reverse bias : n->p

for NMOS: Vsb > 0 RBB, Vth increase
for PMOS:  Vsb > 0 FBB,

Left Graph shows the Current equations at drain of a NMOS in different regions: subthreshold region, linear region, saturation region and velocity-saturation.

1) r_d in the equation of I_D in the subthreshold region is the DIBL factor and also the body effect.

2) K' = u*C_ox

3) (1+lamda*V_ds) is channel modulation

FIFO and LIFO(Updating)

FIFO

1)SYNCHRONOUS and ASYNCHRONOUS;
   If read and write clock domains are governed by same clock signal, whether one clock signal or two clock signals, the FIFO is said to be SYNCHRONOUS;
   If read and write clock domains are not governed by clock signals FIFO is said to be ASYNCHRONOUS. 

2) Here is an example of Implement FIFI using Verilog

3) FIFO Depth Calculation

Traffic Light(Updating)

1) The simple traffic light in a two way road.
     So there are two traffic lights 1 and 2 and each has green 1 and red 0;
                                                T1    T2
                                        S0     0       0
                                        S1     1       0
                                        S2     0       1
   促使state转变的：
1）input （not clock）
2）next clock edge

Delay in the graph is the key in the problem. In this case, we can generate another input signal as input.


2) A more complex traffic light

Multiprocessor cache coherence

Informally, we could say a memory system is coherent if any read of a data item returns the most recently written value of that data item.

The protocols to maintain coherence for multiple processors are called cache coherence protocols. key to implementing a cache coherence protocol is tracking the state of any sharing of a data block.

私有数据被单个处理器使用，而共享数据被多个处理器使用，当共享数据装载到cache中时，会有多个cache中形成副本。

两类协议：
1）目录式：把物理存储器的共享状态存放在一个地点，成为目录。
2）监听式：每个含有物理存储器中书记块副本的cache还要保留该数据块共享状态的副本，但是并不集中的保存状态，cache通常可以通过广播没接访问，所有的cache控制器对总线进行监视或监听，来确定它们是否含有总线或交换机上请求的数据块的副本。

Latch and Flip-Flop Design

Latch
Function: Data will be transferred as long as the clk is at positive high.

Graph 1) is the basic MUX-based Latch

Graph 2) has an additional keeper .
    The feedback inverter should be smaller to enable faster propagation of D

Graph 3) is the back-driving version.
    Also called TG-Latch
    Clk=1: D is transferred to A and then Q;
    Clk=0: D can't be propagate, old value is stored at A;
    No write conflict;
    The inverter at D is used for input noice protection.

Graph 4) used when the output is driven to noisy circuits.

Graph 1) to 4) are all static Latch.

Graph 5) is Dynamic Latch.

Take a look the waveform of clk, D and Q, the setup/hold time is w.r.t. the closing CLK edge!











Flip-Flop
Function: Data will be transferred at only one or both of the clk edges.

Graph 1) a pair of back to back latches, note the fi and fi_bar in the first graph should be exchanged.

Graph 2) The Master-Slave Latch Pair(MS Flip-Flop).
    Clk=0: master passes D to S;
    Clk=1: slave passes S to Q;
    D arrives just before clk: 0->1

Graph 3) The block representation of the pulse triggered Latch. (Need to be better analyzed)

Graph 4)The waveform of a flip-flop. The setup and hold time are all w.r.t. the rising edge if it is a posedge triggered flip-flop.



















Important Knowledge
Two ways are usually used to build storage elements:
1) using positive feedback to keep the value;
2) using capacitance to dynamically store the value;
    Adv  : faster
    Disad: less robust, sensitive to noise, particularly charge injection and charge sharing;
(Need to know what is charge sharing)

Reference: Course Notes